1. Field of the Invention
The present invention relates to an improved switch configuration, and in particular an improved switch configuration having an improved power supply rejection ratio (PSRR).
2. Discussion of the Related Art
In order to avoid noise at the output of an amplification system, it is desirable to increase the PSRR (Power Supply Rejection Ratio). The PSRR is a measure of the influence of power supply ripple at the output of the system.
Referring to FIG. 1, an inverting amplifier is shown comprising an operational amplifier 2, and a number of resistors. The output of operational amplifier 2 is connected to an output node 4. The operational amplifier 2 further comprises a negative input 6 and a positive input 8, the positive input 8 connected to a ground node 10. The negative input 6 of the operational amplifier is connected to one node of a resistor 12, the second node of resistor 12 being connected to an input node 14 of the circuit. The operational amplifier is provided with a feedback path from output 4 to the negative input node 6 comprising first and second feedback resistors 16, 18, arranged in series. A switch 20 is connected in parallel with the second feedback resistor 18, thus allowing the second feedback resistor 18 to be bypassed, reducing the total feedback resistance to the resistance of the first feedback resistor 16. In this way the gain of the amplifier system can be changed.
Switch 20 can be implemented using MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) as shown in FIG. 2. With reference to FIG. 2, the switch comprises an input node 22, which is connected to the node between the first and second feedback resistors 16, 18 of FIG. 1, and a output node 4 which is the output node of the amplifier system of FIG. 1. Switch 20 comprises a P-channel MOS transistor 24, connected in parallel with a N-channel MOS transistor 26. One of the source/drain nodes of each of the NMOS and PMOS transistors 24 and 26 is connected to input node 22, and the other of the source/drain nodes is connected to output node 4. A first switch control signal Scf on an input line 28 is connected to the gate node of the PMOS transistor 24. A second switch control signal Scfn on an input line 30, which is the inverse of the first switch control signal, is connected to the gate node of the NMOS transistors 26.
Switch 20 is controlled to operate in one of two states. In a first state the first switch control signal on line 28 is high and the second switch control signal on line 26 is low, thus turning off both PMOS transistor 24 and NMOS transistor 26, thereby isolating the input node 22 from the output node 4 so that no current passes between these nodes. In a second state, the first switch control signal on line 28 is low and the second switch control signal on line 30 is high, thus turning on both PMOS transistor 24 and NMOS transistors 26, and thereby connecting the input node 22 to the output node 4.
Switch 20 is disadvantageous due to the parasitic capacitances present between the nodes of the NMOS and PMOS transistors 24, 26. PMOS transistor 24 comprises a well 32 connected to a supply voltage Vdd. There is a parasitic capacitance 34, 40 between the well 32 and each of the source/drain nodes of PMOS transistor 24 respectively and a parasitic capacitance 36, 38 between the gate node and each of the source/drain nodes of PMOS transistor 24 respectively. NMOS transistor 26 comprises parasitic capacitances 42 and 44 between its gate node and each of its source/drain nodes.
Combinations of these parasitic capacitances will be present at the input node 22 or output node 4 of the switch when it is in either of the first or second states. The parasitic capacitance at the input node 22 in particular is disadvantageous as this node is connected, via the first feedback resistor 16, to the sensitive negative input node of the amplifier 2. The well 32 of PMOS transistor 24 and one of the first and second switch control signals on lines 28 and 30 will always be connected to the supply voltage Vdd in each state of the switch, and thus due to the parasitic capacitances 38, 40 and 42, any ripple in this supply voltage will be present at the negative node 6 of the amplifier, and will thus be amplified and will appear at the output node 4. This results in a high PSRR of the amplifier system which causes problems such as noise at the output of the system.